This application claims priority from Korean Patent Application No. 2003-44252, which was filed on Jul. 1, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an in-line integrated circuit chip packaging apparatus and a method for manufacturing in-line integrated circuit chip packages and, more particularly, to an in-line integrated circuit chip packaging apparatus for manufacturing a double-sided stacked multi-chip packages using wire bonding techniques and a method of manufacturing integrated circuit chip packages using the same.
2. Description of the Related Art
The continuing demand for improvements in mobile phones and other personal electronics such as PDAs, MP3 players, digital cameras and notebook computers, has resulting in a corresponding demand for electronic devices that are smaller, lighter, higher capacity and more highly integrated. One method of achieving these requirements involves loading several integrated circuit chips onto a single electronic device using a multi-chip packaging technique. Multi-chip packaging techniques, which produce a single package containing a plurality of individual integrated circuit chips, reduces the size and weight of an electronic device as well as the area required to mount the semiconductor chips within the electronic device.
In a conventional integrated circuit chip packaging process, a lead frame is used for providing electrical connections between the semiconductor chip and an external device. The lead frame is typically manufactured as a strip configured for packaging 8 or 16 semiconductor chips simultaneously.
One multi-chip packaging technique, the stack type loading method, involves loading a plurality of semiconductor chips on both faces of the lead frame. Other multi-chip packaging techniques include both the dual die package (DDP) method which involves stacking of two semiconductor chips, one chip on each face of the lead frame, and the quad die package (QDP) method, which involves stacking four chips, two chips on each face, on the lead frame.
FIG. 1 is a cross-sectional view of a conventional DDP 10. As illustrated in FIG. 1, a conventional DDP 10 typically includes a first semiconductor chip 11 and a second semiconductor chip 13, which are mounted on a lead frame 20 that includes a die pad 21 and a lead finger 23. The first semiconductor chip 11 and the second semiconductor chip 13 are attached on an upper face and a lower face of the die pad 21 using a first bonding layer 25 and a second bonding layer 26, respectively. The first semiconductor chip 11 is electrically connected to the lead finger 23 via a wire bond 27, and the second semiconductor chip 13 is electrically connected to the lead finger 23 via a wire bond 28. The first semiconductor chip 11, the second semiconductor chip 13, and the wire bonds 27 and 28 are protected from an external environment by a plastic molding 31, which is formed from a material such as an epoxy molding compound, which encapsulates and seals the more sensitive portions of the structure.
FIG. 2 is a cross-sectional view of a typical QDP structure. As illustrated in FIG. 2, a conventional QDP 30 includes four semiconductor chips 31, 33, 35, and 37, which are loaded on a lead frame 40 that includes a die pad 41 and a lead finger 43. During the manufacture of a conventional QDP according to FIG. 2, the first and second semiconductor chips 31, 33 are sequentially attached to an upper face of the die pad 41 using first and second bonding layers 45, 47 respectively. Similarly, the third and fourth semiconductor chips 35, 37 will be sequentially attached to a lower face of the die pad 41 using third and fourth bonding layers 46, 48. The first semiconductor chip 31 may then be electrically connected to the lead finger 43 using bonding wires 51 and the second semiconductor chip 33 may be electrically connected to the lead finger using bonding wires 53. Similarly, the third semiconductor chip 35 may be electrically connected to the lead finger 43 using bonding wires 55 and the fourth semiconductor chip 37 may be electrically connected to the lead finger 43 using bonding wires 57.
The four semiconductor chips 31, 33, 35, 37, the corresponding bonding wires 51, 53, 55, and 57, and the bonding regions of the chips and the lead fingers may then be sealed in a plastic molding 61 formed from a material such as an epoxy mold compound (EMC) or other suitable composition.
A method of manufacturing a conventional integrated circuit chip packages such as the DDP and the QDP configurations depicted in FIGS. 1 and 2 typically includes a die attach process for attaching an individual semiconductor chip that has been separated from a wafer to the lead frame or a semiconductor chip that has been previously mounted on the lead frame. A wire bonding process is then used for establishing electrical connections between the semiconductor chip and the lead frame using conductive metal wires. A molding process is then utilized to encapsulate and protect the semiconductor chips, bonding wires and inner portions of the lead frame in a molding resin to protect against environmental contamination or mechanical damage, followed by a trim/form process for cutting and/or bending the exterior portion of the lead finger to obtain a desired lead configuration. Once the individual packages have been completed, they may be subjected to some post-assembly functional, parametric and/or accelerated life testing to evaluate the yield of the assembly process and the reliability of the resulting semiconductor chip packages. Because two semiconductor chips, for DDPs, or four semiconductor chips, for QDPs, are combined in a single package, both the overall area within the electronic device and the mounting area(s) on the circuit substrate can be decreased. Therefore, electronic devices that utilize these techniques and configurations can achieve an improved degree of miniaturization and increase density.
However, conventional apparatuses for manufacturing an integrated circuit chip package typically utilize separate processes and distinct pieces of equipment for the various die attaching, wire bonding and adhesive curing steps. Therefore, when manufacturing a DDP or QDP using a conventional integrated circuit chip package apparatus, an operator must sequentially load the lead frame into and unload the lead frame the die attaching unit, the wire bonding unit, and the curing oven for each semiconductor chip that will be attached to the lead frame. For example, in manufacturing a DDP such as that depicted in FIG. 1, an operator must typically manually transfer the lead frame at least five times since the processes of attaching, oven curing and chip bonding must each be done twice. Similarly, in manufacturing a QDP such as that depicted in FIG. 2, an operator must typically manually transfer the lead frame at least eleven times over the course of performing each of the processes four times in order to mount all four chips.
Therefore, the conventional method of manufacturing multi-chip integrated circuit chip package process is complex, tends to require repeated operator intervention, much of which involves transferring the lead frames of the partially completed devices between various apparatus, and is time-consuming. The convention methods and apparatus, therefore, tend to decrease productivity.